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d a t a sh eet objective speci?cation file under integrated circuits, ic19 1998 jul 07 integrated circuits TZA3044T; tza3044u 1.25 gbits/s gigabit ethernet postamplifiers
1998 jul 07 2 philips semiconductors objective speci?cation 1.25 gbits/s gigabit ethernet postampli?ers TZA3044T; tza3044u features pin compatible with the ne/sa5224 and ne/sa5225 but with extended power supply range and less external component count wideband operation from 1.0 khz to 1.25 ghz typical applicable in 1.25 gbits/s gigabit ethernet receivers single supply voltage from 3.0 to 5.5 v pecl (positive emitter coupled logic) compatible data outputs programmable input signal level-detection to be adjusted using a single external resistor on-chip dc offset compensation without external capacitor fully differential for excellent psrr. applications digital fibre optic receiver for gigabit ethernet applications wideband rf gain block. general description the tza3044 is a high gain limiting amplifier that is designed to process signals from fibre optic preamplifiers like the tza3043. it is pin compatible with the ne/sa5224 and ne/sa5225 but with extended power supply range, and needs less external components. capable of operating at 1.25 gbits/s, the chip has input signal level detection with a user-programmable threshold. the data and level-detection status outputs are differential outputs for optimum noise margin and ease of use. ordering information block diagram type number package name description version TZA3044T so16 plastic small outline package; 16 leads; body width 3.9 mm sot109-1 tza3044u naked die die in waf?e pack carriers; die dimensions 1.58 1.58 mm - fig.1 block diagram. the numbers in brackets refer to the pad numbers of the naked die version. handbook, full pagewidth mgr240 (3, 4, 6, 9) 3 15 (29) (17) 9 16 (30) (1, 14) 1 (11, 12) 6 (13) 7 2 (2, 10, 15, 21, 26) (19, 20, 22, 25) 11 (27, 28) 14 25 k w dc-offset compensation rectifier a1 a2 a3 a4 band gap reference 1 k w tza3044 sub test agnd v cca cf stq (18) 10 st (16) 8 jam (23) 12 doutq (24) 13 dout dgnd v ccd v ref rset 5 (8) dinq 4 (7) din
1998 jul 07 3 philips semiconductors objective speci?cation 1.25 gbits/s gigabit ethernet postampli?ers TZA3044T; tza3044u pinning symbol pin type description sub 1 substrate substrate pin; must be at the same potential as agnd (pin 3) test 2 test pin for test purpose only; to be left open in the application agnd 3 ground analog ground; must be at the same potential as dgnd (pin 11) din 4 analog input differential input; dc bias level is set internally at approximately 2.55 v; complimentary to dinq (pin 5) dinq 5 analog input differential input; dc bias level is set internally at approximately 2.55 v; complimentary to din (pin 4) v cca 6 supply analog supply voltage; must be at the same potential as v ccd (pin 14) cf 7 analog input ?lter capacitor for input signal level detector; capacitor should be connected between this pin and v cca (pin 6) jam 8 pecl input pecl-compatible input; controls the output buffers dout and doutq (pins 13 and 12). when a low signal is applied, the outputs will follow the input signal. when a high signal is applied, the dout and doutq pins will latch into low and high states, respectively. when left unconnected, this pin is actively pulled low (jam off). stq 9 pecl output pecl-compatible status output of the input signal level detector; when the input signal is below the user-programmed threshold level, this output is high; complimentary to st (pin 10) st 10 pecl output pecl-compatible status output of the input signal level detector; when the input signal is below the user-programmed threshold level, this output is low; complimentary to stq (pin 9) dgnd 11 ground digital ground; must be at the same potential as agnd (pin 3) doutq 12 pecl output pecl-compatible differential output; when jam is high, this pin will be forced into a high condition; complimentary to dout (pin 13) dout 13 pecl output pecl-compatible differential output; when jam is high, this pin will be forced into a low condition; complimentary to doutq (pin 12) v ccd 14 supply digital supply voltage; must be at the same potential as v cca (pin 6) v ref 15 analog output band gap reference voltage; typical value is 1.2 v; internal series resistor of 1 k w rset 16 analog input input signal level detector programming; nominal dc voltage is v cca - 1.5 v; threshold level is set by connecting an external resistor between rset and v cca or by forcing a current into rset; default value for this resistor is 180 k w which corresponds with approximately 4 mv (p-p) differential input signal
1998 jul 07 4 philips semiconductors objective speci?cation 1.25 gbits/s gigabit ethernet postampli?ers TZA3044T; tza3044u fig.2 pin configuration. handbook, halfpage TZA3044T mgr241 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 sub test agnd din dinq v cca cf jam stq st dgnd doutq dout v ccd v ref rset pad configuration pad centre locations note 1. coordinates represent the position of the centre of the pad, in m m, with respect to the centre of the die. symbol pad coordinates (1) xy sub 1 - 235.7 +647.8 test 2 - 392.8 +647.8 agnd 3 - 532.8 +647.8 agnd 4 - 647.8 +507.1 n.c. 5 - 647.8 +350.0 agnd 6 - 647.8 +210.0 din 7 - 647.8 +70.0 dinq 8 - 647.8 - 70.0 agnd 9 - 647.8 - 210.0 test 10 - 647.8 - 350.0 v cca 11 - 647.8 - 507.1 v cca 12 - 532.8 - 647.8 cf 13 - 392.8 - 647.8 sub 14 - 235.7 - 647.8 test 15 - 78.6 - 647.8 jam 16 +61.4 - 647.8 stq 17 +218.5 - 647.8 st 18 +375.6 - 647.8 dgnd 19 +532.7 - 647.8 dgnd 20 +647.8 - 507.1 test 21 +647.8 - 350.0 dgnd 22 +647.8 - 210.0 doutq 23 +647.8 - 70.0 dout 24 647.8 70.0 dgnd 25 647.8 210.0 test 26 647.8 350.0 v ccd 27 647.8 507.1 v ccd 28 532.7 647.8 v ref 29 392.7 647.8 rset 30 235.6 647.8 n.c. 31 78.5 647.8 n.c. 32 - 78.6 +647.8
1998 jul 07 5 philips semiconductors objective speci?cation 1.25 gbits/s gigabit ethernet postampli?ers TZA3044T; tza3044u bonding pad locations fig.3 bonding pad locations: tza3044u. (1) typical value. pad size: 90 90 m m. handbook, full pagewidth agnd 4 v ccd 27 test 26 dgnd 25 dout 24 doutq 23 dgnd 22 test 21 dgnd 20 agnd 6 din 7 dinq 8 agnd 9 test 10 v cca 11 n.c. 5 tza3044u 12 v cca 3 agnd 2 test 1 sub 32 n.c. 31 n.c. 30 rset 29 v ref 28 v ccd 13 cf 14 sub 15 test 16 jam 17 stq 18 st 19 dgnd mgr242 1.58 mm (1) 1.58 (1) mm x y 0 0 functional description the tza3044 accepts up to 1.25 gbits/s gigabit ethernet data streams, with amplitudes from 2 mv (p-p) up to 1 v (p-p) single-ended. the input signal will be amplified and limited to differential pecl output levels (see fig.1). the input buffer a1 presents an impedance of approximately 4.5 k w to the data stream on the inputs din and dinq. the input can be used both single-ended and differential, but differential operation is preferred for better performance. because of the high gain of the postamplifier, a very small offset voltage would shift the decision level in such a way that the input sensitivity decreases drastically. therefore a dc offset compensation circuit is implemented in the tza3044, which keeps the input of buffer a3 at its toggle point in the absence of any input signal. an input signal level detection is implemented to check if the input signal is above the user-programmed level. the outcome of this test is available at the pecl outputs st and stq. this flag can also be used to prevent the pecl outputs dout and doutq from reacting to noise in the absence of a valid input signal, by connecting the output stq to the input jam. this insures that data will only be transmitted when the input signal-to-noise ratio is sufficient for low bit error rate system operation. pecl logic the logic level symbol definitions for pecl are shown in fig.4. input biasing the input pins din and dinq are dc biased at approximately 2.55 v by an internal reference generator (see fig.5). the tza3044 can be dc coupled, but ac coupling is preferred. in case of dc coupling, the driving source must operate within the allowable input signal range (2.0 v to v cca + 0.5 v). also a dc offset voltage of
1998 jul 07 6 philips semiconductors objective speci?cation 1.25 gbits/s gigabit ethernet postampli?ers TZA3044T; tza3044u more than a few millivolt should be avoided, since the internal dc offset compensation circuit has a limited correction range. if ac coupling is used to remove any dc compatibility requirement, the coupling capacitors must be large enough to pass the lowest input frequency of interest. for example, 1 nf coupling capacitors react with the internal 4.5 k w input bias resistors to yield a lower - 3db frequency of 35 khz. this then sets a limit on the maximum number of consecutive pulses that can be sensed accurately at the system data rate. capacitor tolerance and resistor variation must be included for an accurate calculation. dc-offset compensation a control loop connected between the inputs of buffer a3 and amplifier a1 (see fig.1) will keep the input of buffer a3 at its toggle point in the absence of any input signal. because of the active offset compensation which is integrated in the tza3044, no external capacitor is required. the loop time constant determines the lower cut-off frequency of the amplifier chain, which is set at approximately 850 hz. input signal level-detection the tza3044 allows for user-programmable input signal level-detection and can automatically disable the switching of the pecl outputs if the input signal is below a set threshold. this prevents the outputs from reacting to noise in the absence of a valid input signal, and insures that data will only be transmitted when the signal-to-noise ratio of the input signal is sufficient for low bit-error-rate system operation. complementary pecl flags (st and stq) indicate whether the input signal is above or below the programmed threshold level. the input signal is amplified and rectified before being compared to a programmable threshold reference. a filter is included to prevent noise spikes from triggering the level-detector. this filter has a nominal 1 m s time constant and additional filtering can be achieved by using an external capacitor between pin cf and v cca (the internal driving impedance nominally is 25 k w ). the resultant signal is then compared to a threshold current through pin rset (see fig.6). this current can be set by connecting an external resistor r detect between pin rset and v cca , or by forcing a current into pin rset. the relationship between the threshold current and the detected input voltage is approximately: (1) i rset 0.002 v din v dinq C () a [] = since the voltage on pin rset is held constant at 1.5 v below v cca , the current flowing into this pin will be: (2) combining these two formulas results in a general formula to calculate r detect for a given input signal level-detection: (3) in this formula, v din and v dinq are in v (p-p). example: detection should occur if the differential voltage of the input signals drops below 4 mv (p-p). in this case, a reference current of 0.002 0.004 = 8 m a should flow into pin rset. this can be set using a current source or simply by connecting a resistor of the appropriate value. the resistor must be connected between v cca and pin rset. in this example the resistor would be: the hysteresis is fixed internally at 3 db electrical. in the example of above, a differential level below 4 mv (p-p) of the input signal will drive pin st to low, and an input signal level above 5.7 mv (p-p) will drive pin st to high. since a jam function is provided which forces the data outputs to a predetermined state (dout = low and doutq = high), the pins stq and jam can be connected to automatically disable the signal transmission when the chip senses that the input signal is below the programmed threshold. response time of the input signal level-detection circuit is determined by the time constant of the input capacitors, together with the filter time constant (1 m s internal plus the additional capacitor at pin cf). pecl output circuits the output circuit of st and stq is given in fig.7 the output circuit of dout and doutq is given in fig.8. some pecl termination schemes are given in fig.9. i rset 1.5 r detect ----------------------- - a [] = r detect 750 v din v dinq C () ----------------------------------------- - w [] = r detect 750 0.004 ---------------- - 187.5 k w ==
1998 jul 07 7 philips semiconductors objective speci?cation 1.25 gbits/s gigabit ethernet postampli?ers TZA3044T; tza3044u handbook, full pagewidth mgr243 v oo v o(max) v oqh v oh v oql v ol v o(min) v o(p-p) v cc fig.4 logic level symbol definitions for pecl. fig.5 data input circuit din and dinq. handbook, full pagewidth mgr244 4.5 k w 4.5 k w v cc dinq din 330 m a 330 m a 2.55 v
1998 jul 07 8 philips semiconductors objective speci?cation 1.25 gbits/s gigabit ethernet postampli?ers TZA3044T; tza3044u fig.6 level-detect input circuit rset. handbook, halfpage mgr245 rset 1.5 v v cc fig.7 pecl output circuit st and stq. handbook, halfpage 10 k w mgr246 st, stq v cc v low v high fig.8 pecl output circuit dout and doutq. handbook, halfpage mgr247 105 w 105 w v cc doutq dout 0.5 ma 9 ma 0.5 ma
1998 jul 07 9 philips semiconductors objective speci?cation 1.25 gbits/s gigabit ethernet postampli?ers TZA3044T; tza3044u fig.9 pecl output termination schemes. handbook, full pagewidth v oq v o v iq v i r1 = 50 w r1 = 50 w z o = 50 w v cc - 2 v mgr248 handbook, full pagewidth v oq v o v iq v i r1 = 83.3 w r2 = 125 w r1 = 83.3 w r2 = 125 w z o = 50 w gnd v cc = 5.0 v mgr250 handbook, full pagewidth v oq v o v iq v i z o = 50 w gnd v cc = 3.3 v mgr249 r1 = 127 w r2 = 82.5 w r1 = 127 w r2 = 82.5 w
1998 jul 07 10 philips semiconductors objective speci?cation 1.25 gbits/s gigabit ethernet postampli?ers TZA3044T; tza3044u limiting values in accordance with the absolute maximum rating system (iec 134). note 1. the numbers in brackets refer to the pad numbers of the naked die version. thermal characteristics symbol parameter conditions min. max. unit v cc supply voltage - 0.5 +6 v v n dc voltage note 1 pins 4 and 5 (7 and 8): din and dinq - 0.5 v cc + 0.5 v pin 7 (13): cf - 0.5 v cc + 0.5 v pin 8 (16): jam - 0.5 v cc + 0.5 v pins 9, 10, 12 and 13 (17, 18, 23 and 24): stq, st, doutq and dout v cc - 2v cc + 0.5 v pin 15 (29): v ref - 0.5 +3.2 v pin 16 (30): rset - 0.5 v cc + 0.5 v i n dc current note 1 pin 4 and 5 (7 and 8): din and dinq - 1+1ma pin 7 (13): cf - 1+1ma pin 8 (16): jam - 1+1ma pins 9, 10, 12 and 13 (17, 18, 23 and 24): stq, st, doutq and dout - 25 +10 ma pin 15 (29): v ref - 2 +2.5 ma pin 16 (30): rset - 2+2ma p tot total power dissipation - tbf mw t stg storage temperature - 65 +150 c t j junction temperature - 150 c t amb ambient temperature - 40 +85 c symbol parameter value unit r th(j-s) thermal resistance from junction to solder point tbf k/w r th(j-a) thermal resistance from junction to ambient tbf k/w
1998 jul 07 11 philips semiconductors objective speci?cation 1.25 gbits/s gigabit ethernet postampli?ers TZA3044T; tza3044u characteristics for typical values t amb =25 c and v cc = 3.3 v; minimum and maximum values are valid over the entire ambient temperature range and supply voltage range; all voltages with respect to ground; unless otherwise speci?ed. symbol parameter conditions min. typ. max. unit supply v cc supply voltage 3 3.3 5.5 v i ccd digital supply current note 1 - 18 27 ma i cca analog supply current - 15 22 ma p tot total power dissipation note 1 - 110 270 mw t j junction temperature - 40 - +120 c t amb ambient temperature - 40 +25 +85 c inputs: din and dinq v i(se)(p-p) input signal voltage single-ended (peak-to-peak) 0.002 - 1.0 v v i(dif)(p-p) input signal voltage differential (peak-to-peak) 0.004 - 2.0 v v i absolute input signal voltage 2.1 2.55 v cca + 0.5 v v io(eq) equivalent input signal offset voltage -- 50 m v v io(cor) input offset voltage correction range note 2 - 5 - +5 mv r i input resistance single-ended 2.9 4.5 7.6 k w c i input capacitance single-ended -- 2.5 pf v n(i)(rms) equivalent input rms noise voltage note 3 - 115 145 m v input signal level-detect: rset i ref reference current note 4 5 - 60 m a v ref reference voltage referred to v cca - 1.55 - 1.5 - 1.45 v v th(p-p) programmability (single-ended, peak-to-peak) v i = 200 khz square wave 2 - 12 mv hys hysteresis electrically measured 2 3 4 db r f ?lter resistance 14 25 41 k w t f ?lter time constant cf = 0 0.5 1.0 2.0 m s pecl outputs: dout and doutq v ol low-level output voltage r l =50 w to v cc - 2v v cc - 1840 - v cc - 1620 mv v oh high-level output voltage r l =50 w to v cc - 2v v cc - 1100 - v cc - 900 mv t r rise time 20% to 80% - 150 250 ps t f fall time 80% to 20% - 100 200 ps t w(p-p) pulse width distortion -- 30 ps f -3db(l) low frequency - 3 db point - 0.85 1.5 khz f -3db(h) high frequency - 3 db point 1000 1300 1600 mhz
1998 jul 07 12 philips semiconductors objective speci?cation 1.25 gbits/s gigabit ethernet postampli?ers TZA3044T; tza3044u notes 1. dout, doutq, st and stq outputs are left unconnected. 2. if the input is dc coupled, the preceding amplifiers output offset voltage should not exceed these limits, in order to avoid malfunctioning of the dc offset compensation circuit. 3. 4. the reference currents can be set by a resistor between v cca and pin rset. the corresponding input signal level-detect range is from 2 to 12 mv (p-p) single-ended. see section input signal level-detection for detailed information. 5. internal pull-down resistor of 500 k w to dgnd. 6. internal series resistor of 1 k w . pecl outputs: st and stq v ol low-level output voltage r l =50 w to v cc - 2v v cc - 1840 - v cc - 1620 mv v oh high-level output voltage r l =50 w to v cc - 2v v cc - 1100 - v cc - 900 mv t r rise time 20% to 80% -- 600 ns t f fall time 80% to 20% -- 200 ns pecl input: jam v il low-level input voltage -- v cc - 1490 mv v ih high-level input voltage v cc - 1165 -- mv i i(jam) jam input current note 5 - 10 - +10 m a reference voltage output: v ref v ref reference voltage note 6 1.165 1.20 1.235 v symbol parameter conditions min. typ. max. unit input rms noise total output rms noise low frequency gain ------------------------------------------------------------ =
1998 jul 07 13 philips semiconductors objective speci?cation 1.25 gbits/s gigabit ethernet postampli?ers TZA3044T; tza3044u application information fig.10 application diagram. handbook, full pagewidth mgr251 (23) 12 doutq (24) 13 dout 1 k w 50 w 50 w 10 nf 10 nf 100 nf 180 k w tza3044 (1, 14) 1 (19, 20, 22, 25) 11 sub (16) 8 jam (17) 9 stq (18) 10 st (3, 4, 6, 9) 3 agnd v cc 6 (11, 12) v cca 16 (30) rset 7 (13) cf 15 (29) v ref 14 (27, 28) v ccd dgnd data out data in level-detect status v cc - 2 v 5 (8) dinq 4 (7) din 100 nf the numbers in brackets refer to the pad numbers of the naked die version.
1998 jul 07 14 philips semiconductors objective speci?cation 1.25 gbits/s gigabit ethernet postampli?ers TZA3044T; tza3044u this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader .this text is here in _ white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader.this text is here in this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader. white to force land scape pages to be ... w idth mgr252 (23) 12 doutq 6 out 7 outq (24) 13 dout 1 k w 50 w 50 w 10 nf 10 nf 100 nf 4 pf noise filter: 1-pole, 800 mhz 100 w 180 k w tza3043t tza3044 (1, 14) 1 (19, 20, 22, 25) 11 sub (16) 8 jam (17) 9 stq (18) 10 st (3, 4, 6, 9) 3 agnd 8 v cc v cc 6 (11, 12) v cca 16 (30) rset 7 (13) cf 15 (29) v ref 14 (27, 28) v ccd dgnd data out level-detect status v cc - 2 v 5 (8) dinq 4 (7) din 3 iphoto 1 dref 22 nf 680 nf 100 nf (1) (1) (1) 2 gnd 4 gnd 5 gnd fig.11 stm1 receiver using the tza3043t and tza3044. (1) ferrite bead e.g. murata blm31a601s. the numbers in brackets refer to the pad numbers of the naked die version.
1998 jul 07 15 philips semiconductors objective speci?cation 1.25 gbits/s gigabit ethernet postampli?ers TZA3044T; tza3044u package outline x w m q a a 1 a 2 b p d h e l p q detail x e z e c l v m a (a ) 3 a 8 9 1 16 y pin 1 index unit a max. a 1 a 2 a 3 b p cd (1) e (1) (1) eh e ll p qz y w v q references outline version european projection issue date iec jedec eiaj mm inches 1.75 0.25 0.10 1.45 1.25 0.25 0.49 0.36 0.25 0.19 10.0 9.8 4.0 3.8 1.27 6.2 5.8 0.7 0.6 0.7 0.3 8 0 o o 0.25 0.1 dimensions (inch dimensions are derived from the original mm dimensions) note 1. plastic or metal protrusions of 0.15 mm maximum per side are not included. 1.0 0.4 sot109-1 95-01-23 97-05-22 076e07s ms-012ac 0.069 0.010 0.004 0.057 0.049 0.01 0.019 0.014 0.0100 0.0075 0.39 0.38 0.16 0.15 0.050 1.05 0.041 0.244 0.228 0.028 0.020 0.028 0.012 0.01 0.25 0.01 0.004 0.039 0.016 0 2.5 5 mm scale so16: plastic small outline package; 16 leads; body width 3.9 mm sot109-1
1998 jul 07 16 philips semiconductors objective speci?cation 1.25 gbits/s gigabit ethernet postampli?ers TZA3044T; tza3044u soldering introduction there is no soldering method that is ideal for all ic packages. wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. however, wave soldering is not always suitable for surface mounted ics, or for printed-circuits with high population densities. in these situations reflow soldering is often used. this text gives a very brief insight to a complex technology. a more in-depth account of soldering ics can be found in our data handbook ic26; integrated circuit packages (order code 9398 652 90011). re?ow soldering reflow soldering techniques are suitable for all so packages. reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. several techniques exist for reflowing; for example, thermal conduction by heated belt. dwell times vary between 50 and 300 seconds depending on heating method. typical reflow temperatures range from 215 to 250 c. preheating is necessary to dry the paste and evaporate the binding agent. preheating duration: 45 minutes at 45 c. wave soldering wave soldering techniques can be used for all so packages if the following conditions are observed: a double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. the longitudinal axis of the package footprint must be parallel to the solder flow. the package footprint must incorporate solder thieves at the downstream end. during placement and before soldering, the package must be fixed with a droplet of adhesive. the adhesive can be applied by screen printing, pin transfer or syringe dispensing. the package can be soldered after the adhesive is cured. maximum permissible solder temperature is 260 c, and maximum duration of package immersion in solder is 10 seconds, if cooled to less than 150 c within 6 seconds. typical dwell time is 4 seconds at 250 c. a mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. repairing soldered joints fix the component by first soldering two diagonally- opposite end leads. use only a low voltage soldering iron (less than 24 v) applied to the flat part of the lead. contact time must be limited to 10 seconds at up to 300 c. when using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 c.
1998 jul 07 17 philips semiconductors objective speci?cation 1.25 gbits/s gigabit ethernet postampli?ers TZA3044T; tza3044u definitions life support applications these products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify philips for any damages resulting from such improper use or sale. data sheet status objective speci?cation this data sheet contains target or goal speci?cations for product development. preliminary speci?cation this data sheet contains preliminary data; supplementary data may be published later. product speci?cation this data sheet contains ?nal product speci?cations. limiting values limiting values given are in accordance with the absolute maximum rating system (iec 134). stress above one or more of the limiting values may cause permanent damage to the device. these are stress ratings only and operation of the device at these or at any other conditions above those given in the characteristics sections of the speci?cation is not implied. exposure to limiting values for extended periods may affect device reliability. application information where application information is given, it is advisory and does not form part of the speci?cation.
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philippines inc., 106 valero st. salcedo village, p.o. box 2108 mcc, makati, metro manila, tel. +63 2 816 6380, fax. +63 2 817 3474 poland: ul. lukiska 10, pl 04-123 warszawa, tel. +48 22 612 2831, fax. +48 22 612 2327 portugal: see spain romania: see italy russia: philips russia, ul. usatcheva 35a, 119048 moscow, tel. +7 095 755 6918, fax. +7 095 755 6919 singapore: lorong 1, toa payoh, singapore 319762, tel. +65 350 2538, fax. +65 251 6500 slovakia: see austria slovenia: see italy south africa: s.a. philips pty ltd., 195-215 main road martindale, 2092 johannesburg, p.o. box 7430 johannesburg 2000, tel. +27 11 470 5911, fax. +27 11 470 5494 south america: al. vicente pinzon, 173, 6th floor, 04547-130 s?o paulo, sp, brazil, tel. +55 11 821 2333, fax. +55 11 821 2382 spain: balmes 22, 08007 barcelona, tel. +34 93 301 6312, fax. +34 93 301 4107 sweden: kottbygatan 7, akalla, s-16485 stockholm, tel. +46 8 5985 2000, fax. +46 8 5985 2745 switzerland: allmendstrasse 140, ch-8027 zrich, tel. +41 1 488 2741 fax. +41 1 488 3263 taiwan: philips semiconductors, 6f, no. 96, chien kuo n. rd., sec. 1, taipei, taiwan tel. +886 2 2134 2865, fax. +886 2 2134 2874 thailand: philips electronics (thailand) ltd., 209/2 sanpavuth-bangna road prakanong, bangkok 10260, tel. +66 2 745 4090, fax. +66 2 398 0793 turkey: talatpasa cad. no. 5, 80640 gltepe/istanbul, tel. +90 212 279 2770, fax. +90 212 282 6707 ukraine : philips ukraine, 4 patrice lumumba str., building b, floor 7, 252042 kiev, tel. +380 44 264 2776, fax. +380 44 268 0461 united kingdom: philips semiconductors ltd., 276 bath road, hayes, middlesex ub3 5bx, tel. +44 181 730 5000, fax. +44 181 754 8421 united states: 811 east arques avenue, sunnyvale, ca 94088-3409, tel. +1 800 234 7381 uruguay: see south america vietnam: see singapore yugoslavia: philips, trg n. pasica 5/v, 11000 beograd, tel. +381 11 625 344, fax.+381 11 635 777 for all other countries apply to: philips semiconductors, international marketing & sales communications, building be-p, p.o. box 218, 5600 md eindhoven, the netherlands, fax. +31 40 27 24825 argentina: see south america australia: 34 waterloo road, north ryde, nsw 2113, tel. +61 2 9805 4455, fax. +61 2 9805 4466 austria: computerstr. 6, a-1101 wien, p.o. box 213, tel. +43 160 1010, fax. +43 160 101 1210 belarus: hotel minsk business center, bld. 3, r. 1211, volodarski str. 6, 220050 minsk, tel. +375 172 200 733, fax. +375 172 200 773 belgium: see the netherlands brazil: see south america bulgaria: philips bulgaria ltd., energoproject, 15th floor, 51 james bourchier blvd., 1407 sofia, tel. +359 2 689 211, fax. +359 2 689 102 canada: philips semiconductors/components, tel. +1 800 234 7381 china/hong kong: 501 hong kong industrial technology centre, 72 tat chee avenue, kowloon tong, hong kong, tel. +852 2319 7888, fax. +852 2319 7700 colombia: see south america czech republic: see austria denmark: prags boulevard 80, pb 1919, dk-2300 copenhagen s, tel. +45 32 88 2636, fax. +45 31 57 0044 finland: sinikalliontie 3, fin-02630 espoo, tel. +358 9 615800, fax. +358 9 61580920 france: 51 rue carnot, bp317, 92156 suresnes cedex, tel. +33 1 40 99 6161, fax. +33 1 40 99 6427 germany: hammerbrookstra?e 69, d-20097 hamburg, tel. +49 40 23 53 60, fax. +49 40 23 536 300 greece: no. 15, 25th march street, gr 17778 tavros/athens, tel. +30 1 4894 339/239, fax. +30 1 4814 240 hungary: see austria india: philips india ltd, band box building, 2nd floor, 254-d, dr. annie besant road, worli, mumbai 400 025, tel. +91 22 493 8541, fax. +91 22 493 0966 indonesia: pt philips development corporation, semiconductors division, gedung philips, jl. buncit raya kav.99-100, jakarta 12510, tel. +62 21 794 0040 ext. 2501, fax. +62 21 794 0080 ireland: newstead, clonskeagh, dublin 14, tel. +353 1 7640 000, fax. +353 1 7640 200 israel: rapac electronics, 7 kehilat saloniki st, po box 18053, tel aviv 61180, tel. +972 3 645 0444, fax. +972 3 649 1007 italy: philips semiconductors, piazza iv novembre 3, 20124 milano, tel. +39 2 6752 2531, fax. +39 2 6752 2557 japan: philips bldg 13-37, kohnan 2-chome, minato-ku, tokyo 108-8507, tel. +81 3 3740 5130, fax. +81 3 3740 5077 korea: philips house, 260-199 itaewon-dong, yongsan-ku, seoul, tel. +82 2 709 1412, fax. +82 2 709 1415 malaysia: no. 76 jalan universiti, 46200 petaling jaya, selangor, tel. +60 3 750 5214, fax. +60 3 757 4880 mexico: 5900 gateway east, suite 200, el paso, texas 79905, tel. +9-5 800 234 7381 printed in the netherlands 425102/200/01/pp20 date of release: 1998 jul 07 document order number: 9397 750 03816

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